PLL_APLL (reference) in projects: u-boot

Searched refs:PLL_APLL (Results 1 – 15 of 15) sorted by relevance

/u-boot/board/google/veyron/
A D	veyron.c	`50 clk.id = PLL_APLL; in veyron_init()`
/u-boot/include/dt-bindings/clock/
A D	rk3036-cru.h	`11 #define PLL_APLL 1 macro`
A D	rk3128-cru.h	`10 #define PLL_APLL 1 macro`
A D	rk3228-cru.h	`10 #define PLL_APLL 1 macro`
A D	rk3188-cru-common.h	`11 #define PLL_APLL 1 macro`
A D	rv1108-cru.h	`11 #define PLL_APLL 0 macro`
A D	rk3288-cru.h	`8 #define PLL_APLL 1 macro`
A D	rk3308-cru.h	`11 #define PLL_APLL 1 macro`
A D	rk3328-cru.h	`11 #define PLL_APLL 1 macro`
A D	px30-cru.h	`11 #define PLL_APLL 1 macro`
/u-boot/drivers/clk/rockchip/
A D	clk_rk3308.c	`59 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0), 792 case PLL_APLL: in rk3308_clk_get_rate()`
A D	clk_rk3188.c	`507 case PLL_APLL: in rk3188_clk_set_rate()`
A D	clk_rk3288.c	`800 case PLL_APLL: in rk3288_clk_set_rate()`
A D	clk_px30.c	`1173 case PLL_APLL: in px30_clk_get_rate()`
/u-boot/arch/arm/dts/
A D	rk3328.dtsi	`796 <&cru HDMIPHY>, <&cru PLL_APLL>,`

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