Home
last modified time | relevance | path

Searched refs:PLL_ENABLE_MASK (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/phy/
A Dphy-ti-am654.c62 #define PLL_ENABLE_MASK GENMASK(30, 29) macro
201 u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; in serdes_am654_enable_pll()
212 u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK; in serdes_am654_disable_pll()
/u-boot/arch/arm/mach-tegra/
A Dcpu.c181 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
223 reg |= PLL_ENABLE_MASK; in pllx_set_rate()
A Dclock.c618 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
636 base_reg |= PLL_ENABLE_MASK; in clock_set_rate()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dclk_rst.h244 #define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) macro

Completed in 12 milliseconds