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Searched refs:PLL_MODE_MASK (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/clk/rockchip/
A Dclk_pll.c19 #define PLL_MODE_MASK 0x3 macro
307 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
332 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
A Dclk_rk3368.c75 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { in rkclk_pll_get_rate()
105 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
127 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
A Dclk_rk3399.c97 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, enumerator
343 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
364 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3368.h75 PLL_MODE_MASK = GENMASK(9, 8), enumerator

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