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Searched refs:PLL_POSTDIV1_SHIFT (Results 1 – 12 of 12) sorted by relevance

/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3036.h68 PLL_POSTDIV1_SHIFT = 12, enumerator
69 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
A Dcru_rk3128.h75 PLL_POSTDIV1_SHIFT = 12, enumerator
76 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
A Dcru_rk322x.h70 PLL_POSTDIV1_SHIFT = 12, enumerator
71 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
A Dcru_px30.h119 PLL_POSTDIV1_SHIFT = 12, enumerator
120 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
/u-boot/arch/arm/include/asm/arch-rk3308/
A Dcru_rk3308.h96 PLL_POSTDIV1_SHIFT = 12, enumerator
97 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
/u-boot/drivers/clk/rockchip/
A Dclk_rk3036.c71 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
203 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
A Dclk_rk3328.c55 PLL_POSTDIV1_SHIFT = 12, enumerator
56 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
270 (div->postdiv1 << PLL_POSTDIV1_SHIFT)); in rkclk_set_pll()
A Dclk_rk322x.c70 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
205 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
A Dclk_rk3128.c65 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
270 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
A Dclk_rk3399.c84 PLL_POSTDIV1_SHIFT = 8, enumerator
85 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
356 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
A Dclk_px30.c243 (rate->postdiv1 << PLL_POSTDIV1_SHIFT) | rate->fbdiv); in rkclk_set_pll()
277 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
/u-boot/arch/arm/mach-rockchip/rk3036/
A Dsdram_rk3036.c341 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()

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