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Searched refs:PLL_SRIF_DPLL2_PHASE_SHIFT_SET (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c35 #define PLL_SRIF_DPLL2_PHASE_SHIFT_SET(x) \ macro
230 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG); in qca956x_pll_init()
235 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_PCIE_DPLL2_REG); in qca956x_pll_init()
239 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), in qca956x_pll_init()
244 PLL_SRIF_DPLL2_PLL_PWD_SET(1) | PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), in qca956x_pll_init()

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