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Searched refs:PLL_STOP (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-omap2/omap3/
A Dclock.c239 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_34xx()
292 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_34xx()
345 0x00000007, PLL_STOP); in iva_init_34xx()
491 clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); in dpll4_init_36xx()
532 clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP); in dpll5_init_36xx()
575 clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP); in iva_init_36xx()
/u-boot/arch/arm/include/asm/arch-omap3/
A Dclocks_omap3.h10 #define PLL_STOP 1 /* PER & IVA */ macro

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