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Searched refs:POWER_5VCTRL_ENABLE_DCDC (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/cpu/arm926ejs/mxs/
A Dspl_power_init.c370 POWER_5VCTRL_ENABLE_DCDC)) { in mxs_enable_4p2_dcdc_input()
413 POWER_5VCTRL_ENABLE_DCDC); in mxs_enable_4p2_dcdc_input()
578 writel(POWER_5VCTRL_ENABLE_DCDC, in mxs_power_init_dcdc_4p2_source()
718 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); in mxs_batt_boot()
749 POWER_5VCTRL_ENABLE_DCDC); in mxs_batt_boot()
1003 POWER_5VCTRL_ENABLE_DCDC)) { in mxs_get_vddio_power_source_off()
1038 POWER_5VCTRL_ENABLE_DCDC)) { in mxs_get_vddd_power_source_off()
/u-boot/arch/arm/include/asm/arch-mxs/
A Dregs-power-mx23.h108 #define POWER_5VCTRL_ENABLE_DCDC (1 << 0) macro
A Dregs-power-mx28.h109 #define POWER_5VCTRL_ENABLE_DCDC (1 << 0) macro

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