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Searched refs:PPLL_HZ (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/include/asm/arch-rockchip/
A Dcru_rk3399.h73 #define PPLL_HZ (676*MHz) macro
/u-boot/drivers/clk/rockchip/
A Dclk_rk3399.c60 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
1484 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_i2c_get_pmuclk()
1492 src_clk_div = PPLL_HZ / hz; in rk3399_i2c_set_pmuclk()
1513 return DIV_TO_RATE(PPLL_HZ, src_clk_div); in rk3399_i2c_set_pmuclk()
1524 return DIV_TO_RATE(PPLL_HZ, div); in rk3399_pwm_get_clk()
1534 return PPLL_HZ; in rk3399_pmuclk_get_rate()
1563 return PPLL_HZ; in rk3399_pmuclk_set_rate()
1590 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; in pmuclk_init()

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