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Searched refs:PSC_REG_MDCTL (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-keystone/
A Dpsc.c131 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
134 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
161 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
179 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
183 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
205 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
207 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
256 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
266 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
270 __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_module_keep_in_reset_enabled()
[all …]
A Dddr3.c415 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); in ddr3_err_reset_workaround()
419 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A)); in ddr3_err_reset_workaround()
426 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); in ddr3_err_reset_workaround()
429 PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B)); in ddr3_err_reset_workaround()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dpsc_defs.h27 #define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) macro

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