Home
last modified time | relevance | path

Searched refs:PTR3_TDINIT0 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr3_1333.c82 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
A Dlpddr3_stock.c78 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
A Dddr2_v3s.c79 writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sunxi_dw.h149 #define PTR3_TDINIT0(x) ((x) << 0) macro

Completed in 7 milliseconds