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Searched refs:PUP_DQS_WR (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_hw_training.h152 #define PUP_DQS_WR 0x1 macro
A Dddr3_hw_training.c705 mode_config[DQS_WR_MODE] = PUP_DQS_WR; in ddr3_save_training()
840 } else if (reg == PUP_DQS_WR) { in ddr3_read_training_results()
A Dddr3_dqs.c319 adll_addr = ((is_tx == 1) ? PUP_DQS_WR : PUP_DQS_RD); in ddr3_find_adll_limits()
1313 ddr3_write_pup_reg(PUP_DQS_WR, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()

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