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Searched refs:QCA953X_PLL_CLK_CTRL_REG (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
137 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
149 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
167 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
A Dclk.c42 ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG); in get_clocks()
/u-boot/arch/mips/mach-ath79/include/mach/
A Dar71xx_regs.h440 #define QCA953X_PLL_CLK_CTRL_REG 0x08 macro

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