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Searched refs:QCA956X_GMAC_REG_MR_AN_CTRL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/
A Dreset.c283 writel(BIT(6) | BIT(15) | BIT(8), gregs + QCA956X_GMAC_REG_MR_AN_CTRL); in qca956x_sgmii_setup()
294 writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) & ~BIT(15), in qca956x_sgmii_setup()
295 gregs + QCA956X_GMAC_REG_MR_AN_CTRL); in qca956x_sgmii_setup()
306 writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) | BIT(15), in qca956x_sgmii_setup()
307 gregs + QCA956X_GMAC_REG_MR_AN_CTRL); in qca956x_sgmii_setup()
309 writel(readl(gregs + QCA956X_GMAC_REG_MR_AN_CTRL) & ~BIT(15), in qca956x_sgmii_setup()
310 gregs + QCA956X_GMAC_REG_MR_AN_CTRL); in qca956x_sgmii_setup()
/u-boot/arch/mips/mach-ath79/include/mach/
A Dar71xx_regs.h1331 #define QCA956X_GMAC_REG_MR_AN_CTRL 0x1c macro

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