QCA956X_PLL_DDR_CONFIG_REG (reference) in projects: u-boot

Searched refs:QCA956X_PLL_DDR_CONFIG_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A D	clk.c	`197 set_val(QCA956X_PLL_DDR_CONFIG_REG, _mask, _val) 306 while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000) in qca956x_pll_init() 350 pll = readl(regs + QCA956X_PLL_DDR_CONFIG_REG); in get_clocks()`
/u-boot/arch/mips/mach-ath79/include/mach/
A D	ar71xx_regs.h	`538 #define QCA956X_PLL_DDR_CONFIG_REG 0x08 macro`

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