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Searched refs:QCA956X_SRIF_BB_DPLL2_REG (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c230 PLL_SRIF_DPLL2_PHASE_SHIFT_SET(6), srif_regs + QCA956X_SRIF_BB_DPLL2_REG); in qca956x_pll_init()
/u-boot/arch/mips/mach-ath79/include/mach/
A Dar71xx_regs.h1224 #define QCA956X_SRIF_BB_DPLL2_REG 0x184 macro

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