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Searched refs:QIXIS_PWR_CTL2 (Results 1 – 3 of 3) sorted by relevance

/u-boot/board/freescale/common/
A Darm_sleep.c83 tmp = in_8(qixis_base + QIXIS_PWR_CTL2); in ls1_psci_resume_fixup()
85 out_8(qixis_base + QIXIS_PWR_CTL2, tmp); in ls1_psci_resume_fixup()
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dls102xa_psci.c189 tmp = in_8(qixis_base + QIXIS_PWR_CTL2); in ls1_deep_sleep()
191 out_8(qixis_base + QIXIS_PWR_CTL2, tmp); in ls1_deep_sleep()
/u-boot/include/configs/
A Dls1021aqds.h222 #define QIXIS_PWR_CTL2 0x21 macro

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