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Searched refs:R (Results 1 – 25 of 81) sorted by relevance

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/u-boot/lib/
A Dsha1.c91 #define R(t) ( \ in sha1_process() macro
126 P (E, A, B, C, D, R (16)); in sha1_process()
127 P (D, E, A, B, C, R (17)); in sha1_process()
128 P (C, D, E, A, B, R (18)); in sha1_process()
129 P (B, C, D, E, A, R (19)); in sha1_process()
137 P (A, B, C, D, E, R (20)); in sha1_process()
138 P (E, A, B, C, D, R (21)); in sha1_process()
139 P (D, E, A, B, C, R (22)); in sha1_process()
140 P (C, D, E, A, B, R (23)); in sha1_process()
141 P (B, C, D, E, A, R (24)); in sha1_process()
[all …]
A Dsha256.c93 #define R(t) \ in sha256_process() macro
130 P(A, B, C, D, E, F, G, H, R(16), 0xE49B69C1); in sha256_process()
131 P(H, A, B, C, D, E, F, G, R(17), 0xEFBE4786); in sha256_process()
132 P(G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6); in sha256_process()
133 P(F, G, H, A, B, C, D, E, R(19), 0x240CA1CC); in sha256_process()
134 P(E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F); in sha256_process()
135 P(D, E, F, G, H, A, B, C, R(21), 0x4A7484AA); in sha256_process()
136 P(C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC); in sha256_process()
137 P(B, C, D, E, F, G, H, A, R(23), 0x76F988DA); in sha256_process()
138 P(A, B, C, D, E, F, G, H, R(24), 0x983E5152); in sha256_process()
[all …]
/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dlpss.asl12 Name (_DDN, "Intel(R) PWM Controller")
18 Name (_DDN, "Intel(R) HS-UART Controller #1")
42 Name (_DDN, "Intel(R) SPI Controller #1")
48 Name (_DDN, "Intel(R) SPI Controller #2")
54 Name (_DDN, "Intel(R) SPI Controller #3")
61 Name (_DDN, "Intel(R) I2C Controller #0")
67 Name (_DDN, "Intel(R) I2C Controller #1")
73 Name (_DDN, "Intel(R) I2C Controller #2")
79 Name (_DDN, "Intel(R) I2C Controller #3")
85 Name (_DDN, "Intel(R) I2C Controller #4")
[all …]
A Dpmc_ipc.asl18 Name (_DDN, "Intel(R) IPC1 Controller")
/u-boot/arch/arm/mach-rmobile/
A DKconfig.6482 Support for Renesas R-Car Gen3 Condor platform
88 Support for Renesas R-Car Gen3 Draak platform
94 Support for Renesas R-Car Gen3 Eagle platform
100 Support for Renesas R-Car Gen3 Ebisu platform
111 Support for Renesas R-Car Gen3 platform
122 Support for Renesas R-Car Gen3 ULCB platform
A DKconfig8 bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
12 bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
/u-boot/arch/arm/dts/
A Dstm32mp157c-odyssey-som-u-boot.dtsi100 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
109 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
118 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Dstm32mp15xx-dhcor-u-boot.dtsi138 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
147 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
156 /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
A Dam33xx-u-boot.dtsi3 * Copyright (C) 2019 B&R Industrial Automation GmbH -
A Dstm32mp157a-dk1-u-boot.dtsi137 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
146 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
155 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Dstm32mp157c-ed1-u-boot.dtsi133 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
142 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
151 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
A Dr8a77965-ulcb.dts3 * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
A Dr8a77950-ulcb.dts3 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
A Dr8a77960-ulcb.dts3 * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
A Dstm32mp15xx-dhcom-u-boot.dtsi199 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
208 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
217 /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
A Dr8a77965-salvator-x.dts3 * Device Tree Source for the Salvator-X board with R-Car M3-N
A Dr8a77960-salvator-x.dts3 * Device Tree Source for the Salvator-X board with R-Car M3-W
A Dtegra124-venice2.dts76 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dimmap.c131 uint __iomem *R; in do_iopinfo() local
141 R = &immap->im_cpm.cp_pbdir; in do_iopinfo()
143 binary("PB_DIR", in_be32(R++), PB_NBITS); in do_iopinfo()
145 binary("PB_PAR", in_be32(R++), PB_NBITS); in do_iopinfo()
147 binary("PB_ODR", in_be32(R++), PB_NB_ODR); in do_iopinfo()
149 binary("PB_DAT", in_be32(R++), PB_NBITS); in do_iopinfo()
/u-boot/arch/arm/lib/
A Duldivmod.S151 @ Note: A, B & Q, R are aliases
170 @ Note: A, B and Q, R are aliases
171 @ R = A & (B - 1)
190 @ Mov back C to R
195 @ Note: A, B and Q, R are aliases
196 @ R = A & (B - 1)
230 @ Move C to R
/u-boot/doc/chromium/devkeys/
A Dkernel.keyblock2 ŏ�iHiA*R׷3x�o��}��+فg�?�� T�� �� _
3 …36�\��N�$ [�M��j1�^_�X��)�3�d��;��5�z��˞g�5�i��x��c���fp.��{&����l< R��p����F�i��6��P�I…
/u-boot/doc/
A DREADME.rmobile5 and Cortex-A9/A53/A57 based R-Car[2] family of SoCs. Renesas's RMOBILE/R-Car SoC
72 [2] Renesas R-Car:
/u-boot/arch/x86/cpu/quark/
A Dsmc.c1848 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1850 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1868 for (side_x = L; side_x <= R; side_x++) { in rd_train()
1969 x_coordinate[R][T][ch][rk][bl], in rd_train()
1971 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1984 y_coordinate[R][B][ch][bl], in rd_train()
1985 y_coordinate[R][T][ch][bl], in rd_train()
1990 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
2004 for (side_x = L; side_x <= R; side_x++) { in rd_train()
2160 for (side = L; side <= R; side++) { in wr_train()
[all …]
/u-boot/drivers/tee/optee/
A DKconfig8 ARM TrustZone(R) technology as the underlying hardware isolation
/u-boot/drivers/ddr/altera/
A Dsdram_s10.c28 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) argument

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