Home
last modified time | relevance | path

Searched refs:R8A77970_CLK_S2D1 (Results 1 – 3 of 3) sorted by relevance

/u-boot/drivers/clk/renesas/
A Dr8a77970-cpg-mssr.c101 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
117 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
123 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
124 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
126 DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
127 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
128 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
129 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
130 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
131 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
[all …]
/u-boot/include/dt-bindings/clock/
A Dr8a77970-cpg-mssr.h25 #define R8A77970_CLK_S2D1 9 macro
/u-boot/arch/arm/dts/
A Dr8a77970.dtsi489 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
507 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
525 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
542 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
681 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
699 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
717 <&cpg CPG_CORE R8A77970_CLK_S2D1>,
734 <&cpg CPG_CORE R8A77970_CLK_S2D1>,

Completed in 6 milliseconds