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Searched refs:RCC_CFGR_SW_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/
A Dclk_stm32h7.c35 #define RCC_CFGR_SW_MASK GENMASK(2, 0) macro
422 clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); in configure_clocks()
423 while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) in configure_clocks()
648 source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK; in stm32_clk_get_rate()
A Dclk_stm32f.c46 #define RCC_CFGR_SW_MASK GENMASK(1, 0) macro

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