Searched refs:RCC_MP_AHB4ENSETR (Results 1 – 2 of 2) sorted by relevance
| /u-boot/board/st/stm32mp1/ |
| A D | spl.c | 38 #define RCC_MP_AHB4ENSETR (STM32_RCC_BASE + 0x0A28) in board_debug_uart_init() macro
45 writel(BIT(6), RCC_MP_AHB4ENSETR); in board_debug_uart_init()
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| /u-boot/drivers/clk/ |
| A D | clk_stm32mp1.c | 124 #define RCC_MP_AHB4ENSETR 0xA28 macro
564 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
565 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
566 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
567 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
568 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
569 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
570 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
571 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
572 STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
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