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Searched refs:RCC_PLL1DIVR_DIVN1_MASK (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/clk/
A Dclk_stm32h7.c52 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0) macro
534 divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; in stm32_get_PLL1_rate()

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