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Searched refs:RCC_PLL1DIVR_DIVP1_SHIFT (Results 1 – 1 of 1) sorted by relevance

/u-boot/drivers/clk/
A Dclk_stm32h7.c54 #define RCC_PLL1DIVR_DIVP1_SHIFT 9 macro
404 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()
537 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; in stm32_get_PLL1_rate()

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