/u-boot/drivers/video/ |
A D | tda19988.c | 21 #define REG(page, addr) (((page) << 8) | (addr)) macro 29 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 37 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 38 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 57 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 58 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 96 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 101 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 102 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 103 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ [all …]
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/u-boot/drivers/i2c/ |
A D | davinci_i2c.c | 36 REG(&(i2c_base->i2c_con)) = 0;\ 83 REG(&(i2c_base->i2c_drr)); in _flush_rx() 99 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); in _davinci_i2c_setspeed() 108 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_init() 115 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_init() 219 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_read() 220 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_read() 301 REG(&(i2c_base->i2c_cnt)) = 0; in _davinci_i2c_write() 302 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_write() 314 REG(&(i2c_base->i2c_con)) = 0; in _davinci_i2c_probe_chip() [all …]
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/u-boot/lib/dhry/ |
A D | dhry_2.c | 45 #ifndef REG 46 #define REG macro 120 REG One_Fifty Int_Index; 121 REG One_Fifty Int_Loc; 168 REG One_Thirty Int_Loc;
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A D | dhry_1.c | 71 #ifndef REG 73 #define REG macro 99 void Proc_1 (REG Rec_Pointer Ptr_Val_Par); 116 REG One_Fifty Int_2_Loc; in dhry() 118 REG char Ch_Index; in dhry() 327 void Proc_1 (REG Rec_Pointer Ptr_Val_Par) in Proc_1() 330 REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; in Proc_1()
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/u-boot/arch/arm/include/asm/arch-tegra/ |
A D | ap.h | 20 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
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/u-boot/include/ |
A D | sym53c8xx.h | 222 #define REG(r) (r) macro 388 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 391 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 394 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 460 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 463 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
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/u-boot/arch/arm/mach-tegra/ |
A D | cpu.h | 31 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) argument
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A D | pinmux-common.c | 98 #define MUX_REG(pin) REG(pin) 101 #define PULL_REG(pin) REG(pin) 104 #define TRI_REG(pin) REG(pin) 235 u32 *reg = REG(pin); in pinmux_set_io() 257 u32 *reg = REG(pin); in pinmux_set_lock() 284 u32 *reg = REG(pin); in pinmux_set_od() 309 u32 *reg = REG(pin); in pinmux_set_ioreset() 334 u32 *reg = REG(pin); in pinmux_set_rcv_sel() 359 u32 *reg = REG(pin); in pinmux_set_e_io_hv() 383 u32 *reg = REG(grp); in pinmux_set_schmt() [all …]
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/u-boot/board/davinci/da8xxevm/ |
A D | da850evm.c | 441 temp = REG(GPIO_BANK2_REG_SET_ADDR); in rmii_hw_init() 443 REG(GPIO_BANK2_REG_SET_ADDR) = temp; in rmii_hw_init() 446 temp = REG(GPIO_BANK2_REG_DIR_ADDR); in rmii_hw_init() 448 REG(GPIO_BANK2_REG_DIR_ADDR) = temp; in rmii_hw_init()
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A D | omapl138_lcdk.c | 277 if ((REG(CHIP_REV_ID_REG) & 0x3f) == 0x10) in dspwake() 288 REG(HOST1CFG) = DAVINCI_L3CBARAM_BASE; in dspwake() 291 REG(PSC0_MDCTL + (15 * 4)) |= 0x100; in dspwake()
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/u-boot/drivers/net/ |
A D | mcfmii.c | 34 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument 35 (REG & 0x1f) << 18)) 36 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument 37 (REG & 0x1f) << 18) | (VAL & 0xffff))
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A D | mpc8xx_fec.c | 705 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ argument 706 (REG & 0x1f) << 18)) 708 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ argument 709 (REG & 0x1f) << 18) | \
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/u-boot/arch/arm/mach-davinci/include/mach/ |
A D | hardware.h | 18 #define REG(addr) (*(volatile unsigned int *)(addr)) macro 394 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da830() 401 unsigned int jtag_id = REG(JTAG_ID_REG); in cpu_is_da850() 409 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? in get_async3_src()
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/u-boot/drivers/ram/k3-j721e/ |
A D | k3-j721e-ddrss.c | 63 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\ argument 64 char *i, *pstr= xstr(REG); offset = 0;\
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/u-boot/arch/arm/mach-keystone/include/mach/ |
A D | hardware.h | 19 #define REG(addr) (*(volatile unsigned int *)(addr)) macro
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/u-boot/arch/arm/mach-davinci/ |
A D | da850_lowlevel.c | 25 REG(UART0_PWREMU_MGMT) = 0x00006001; in davinci_enable_uart0()
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/u-boot/drivers/mmc/ |
A D | davinci_mmc.c | 23 #define get_val(addr) REG(addr) 24 #define set_val(addr, val) REG(addr) = (val)
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/u-boot/arch/arm/dts/ |
A D | am5729-beagleboneai.dts | 155 reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ 156 <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */
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/u-boot/doc/ |
A D | README.armada-secureboot | 111 | | REG header(s) | |
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