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Searched refs:REG_DDR_IO_CLK_RATIO_OFFS (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_dfs.c351 reg = reg_read(REG_DDR_IO_ADDR) & ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_high_2_low()
638 reg = reg_read(REG_DDR_IO_ADDR) & ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_high_2_low()
957 (1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_low_2_high()
964 ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_low_2_high()
1261 (1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_low_2_high()
1265 ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_low_2_high()
A Dddr3_axp.h185 #define REG_DDR_IO_CLK_RATIO_OFFS 15 macro
A Dddr3_spd.c690 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
963 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
1083 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
A Dddr3_init.c537 (1 << REG_DDR_IO_CLK_RATIO_OFFS))) { in ddr3_init_main()
A Dddr3_hw_training.c172 if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS)) in ddr3_hw_training()

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