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Searched refs:REG_DRAM_PHY_CONFIG_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_dfs.c642 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_high_2_low()
647 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_high_2_low()
1017 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1023 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1367 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_low_2_high()
1381 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
A Dddr3_axp.h290 #define REG_DRAM_PHY_CONFIG_MASK 0x3FFFFFFF macro

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