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Searched refs:REG_DRAM_TRAINING_2_RL_MODE_OFFS (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_axp.h234 #define REG_DRAM_TRAINING_2_RL_MODE_OFFS 3 macro
A Dddr3_read_leveling.c191 reg &= ~(1 << REG_DRAM_TRAINING_2_RL_MODE_OFFS); in ddr3_read_leveling_sw()
322 reg = (reg | (0x1 << REG_DRAM_TRAINING_2_RL_MODE_OFFS)); in ddr3_read_leveling_sw()

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