REG_DRAM_TRAINING_2_WL_MODE_OFFS (reference) in projects: u-boot

Searched refs:REG_DRAM_TRAINING_2_WL_MODE_OFFS (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A D	ddr3_write_leveling.c	`715 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw() 826 reg \|= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw() 950 ~(1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw_reg_dimm() 1058 reg \|= (1 << REG_DRAM_TRAINING_2_WL_MODE_OFFS); in ddr3_write_leveling_sw_reg_dimm()`
A D	ddr3_axp.h	`235 #define REG_DRAM_TRAINING_2_WL_MODE_OFFS 2 macro`

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