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Searched refs:REG_DRAM_TRAINING_WL_OFFS (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_axp.h213 #define REG_DRAM_TRAINING_WL_OFFS 3 macro
A Dddr3_write_leveling.c85 reg = 1 << REG_DRAM_TRAINING_WL_OFFS; in ddr3_write_leveling_hw()
508 reg = (1 << REG_DRAM_TRAINING_WL_OFFS); in ddr3_write_leveling_hw_reg_dimm()

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