Home
last modified time | relevance | path

Searched refs:REG_PHY_CS_OFFS (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_hw_training.c558 reg |= ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
582 reg |= ((0x4 * cs + mode + 1) << REG_PHY_CS_OFFS); in ddr3_write_pup_reg()
604 ((0x4 * cs + mode) << REG_PHY_CS_OFFS); in ddr3_read_pup_reg()
826 reg = (val >> REG_PHY_CS_OFFS) & 0x3F; /*read the phy address */ in ddr3_read_training_results()
A Dddr3_axp.h309 #define REG_PHY_CS_OFFS 16 macro
A Dddr3_write_leveling.c1357 reg |= (reg_addr << REG_PHY_CS_OFFS); in ddr3_write_ctrl_pup_reg()
A Dddr3_pbs.c1517 reg |= ((0x4 * cs + PUP_WL_MODE) << REG_PHY_CS_OFFS); in ddr3_pbs_write_pup_dqs_reg()

Completed in 10 milliseconds