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Searched refs:REG_READ_DATA_READY_DELAYS_ADDR (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c152 reg_read(REG_READ_DATA_READY_DELAYS_ADDR) & in ddr3_read_leveling_hw()
228 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_sw()
240 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
667 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
672 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
723 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
727 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_single_cs_rl_mode()
1069 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1074 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_read_leveling_single_cs_window_mode()
1196 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_read_leveling_single_cs_window_mode()
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A Dddr3_dfs.c715 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_dfs_high_2_low()
719 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_dfs_high_2_low()
1516 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_dfs_low_2_high()
1521 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_dfs_low_2_high()
A Dddr3_axp.h202 #define REG_READ_DATA_READY_DELAYS_ADDR 0x153C macro
A Dddr3_hw_training.c770 *sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_save_training()
859 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, val); /* reg 0x153c */ in ddr3_read_training_results()
A Dddr3_init.c115 debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR); in print_dunit_setup()
A Dddr3_spd.c1053 reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg);

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