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Searched refs:REG_READ_DATA_SAMPLE_DELAYS_ADDR (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c155 reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR) & in ddr3_read_leveling_hw()
220 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_sw()
225 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_read_leveling_sw()
617 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_single_cs_rl_mode()
624 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_rl_mode()
1022 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_read_leveling_single_cs_window_mode()
1029 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_dfs.c708 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_high_2_low()
712 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_high_2_low()
1508 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_low_2_high()
1513 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_low_2_high()
A Dddr3_hw_training.c766 *sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_save_training()
857 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, val); /* reg 0x1538 */ in ddr3_read_training_results()
1093 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_odt_read_dynamic_config()
A Dddr3_axp.h198 #define REG_READ_DATA_SAMPLE_DELAYS_ADDR 0x1538 macro
A Dddr3_init.c114 debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in print_dunit_setup()
A Dddr3_spd.c1041 reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg);

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