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Searched refs:RESET (Results 1 – 25 of 50) sorted by relevance

12

/u-boot/drivers/clk/sunxi/
A Dclk_h616.c60 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
61 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
62 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
64 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
71 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
72 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
77 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
79 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
81 [RST_USB_PHY2] = RESET(0xa78, BIT(30)),
83 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
[all …]
A Dclk_r40.c58 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
59 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
60 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
62 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
63 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
64 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
65 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
66 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
67 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
68 [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
[all …]
A Dclk_a31.c54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
58 [RST_AHB1_MMC0] = RESET(0x2c0, BIT(8)),
59 [RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
60 [RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
61 [RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
62 [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
63 [RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
64 [RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
[all …]
A Dclk_h3.c54 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
55 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
56 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
57 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
59 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
60 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
61 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
62 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
63 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
65 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[all …]
A Dclk_a64.c51 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
52 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
53 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
54 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
55 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
56 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
63 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
64 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
65 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
66 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
[all …]
A Dclk_h6.c51 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
52 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
53 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
59 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
60 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
62 [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
64 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
66 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
68 [RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
69 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
[all …]
A Dclk_a83t.c45 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
46 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
47 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
49 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
50 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
51 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
52 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
53 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
54 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
55 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[all …]
A Dclk_a23.c43 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
44 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
45 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
47 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
48 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
49 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
50 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
51 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
52 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
53 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[all …]
A Dclk_v3s.c33 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
35 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
36 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
37 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
38 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
39 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
41 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
42 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
43 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
A Dclk_a80.c37 [RST_BUS_MMC] = RESET(0x5a0, BIT(8)),
38 [RST_BUS_SPI0] = RESET(0x5a0, BIT(20)),
39 [RST_BUS_SPI1] = RESET(0x5a0, BIT(21)),
40 [RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
41 [RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
43 [RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
44 [RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
45 [RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
46 [RST_BUS_UART3] = RESET(0x5b4, BIT(19)),
47 [RST_BUS_UART4] = RESET(0x5b4, BIT(20)),
[all …]
A Dclk_a10.c55 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
56 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
57 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
A Dclk_a10s.c43 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
44 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
/u-boot/arch/arm/mach-exynos/
A Dsec_boot.S88 .word 0x1 @ CPU0_STATE : RESET
89 .word 0x2 @ CPU1_STATE : SECONDARY RESET
90 .word 0x2 @ CPU2_STATE : SECONDARY RESET
91 .word 0x2 @ CPU3_STATE : SECONDARY RESET
/u-boot/tools/patman/
A Dterminal.py208 RESET = '\033[0m' variable in Color
247 return self.RESET
270 return start + text + self.RESET
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dccu.h55 #define RESET(_off, _bit) { \ macro
/u-boot/drivers/rtc/
A Dds1302.c19 #define RESET rtc_go_low(RST), rtc_go_low(SCLK) macro
165 RESET; in read_ser_drv()
185 RESET; in write_ser_drv()
/u-boot/drivers/fpga/
A Divm_core.c252 { RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */
253 { RESET, IDLE, 0x00, 1 },
254 { RESET, DRPAUSE, 0x50, 5 },
255 { RESET, IRPAUSE, 0x68, 6 },
256 { IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */
259 { DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */
263 { IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */
334 case RESET: in GetState()
2442 (cNextJTAGState != RESET)) { in ispVMStateMachine()
2497 ispVMStateMachine(RESET); /*step devices to RESET state*/ in ispVMStart()
[all …]
/u-boot/board/freescale/mx28evk/
A DREADME20 * JTAG PSWITCH RESET: To the right (reset disabled)
29 * JTAG PSWITCH RESET: To the right (reset disabled)
/u-boot/board/rockchip/evb_rv1108/
A DREADME17 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/u-boot/board/rockchip/sheep_rk3368/
A DREADME23 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/u-boot/include/
A Dlattice.h29 #define RESET 0x00 macro
/u-boot/board/rockchip/evb_rk3399/
A DREADME105 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
113 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/u-boot/doc/
A DREADME.bus_vcxk53 RESET
/u-boot/board/rockchip/evb_rk3328/
A DREADME66 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
/u-boot/board/vamrs/rock960_rk3399/
A DREADME105 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
113 Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:

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