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Searched refs:RXACTIVE (Results 1 – 22 of 22) sorted by relevance

/u-boot/board/siemens/draco/
A Dmux.c34 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
36 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
229 {OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
230 {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
231 {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
233 {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
234 {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
235 {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
240 {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
242 {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
[all …]
/u-boot/board/siemens/rut/
A Dmux.c55 {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
56 {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
57 {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
58 {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
59 {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
60 {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
61 {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
62 {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
63 {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
64 {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
[all …]
/u-boot/board/ti/am335x/
A Dmux.c112 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
114 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
120 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
122 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
129 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
132 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
168 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
175 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
176 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
177 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
[all …]
/u-boot/board/ti/am43xx/
A Dmux.c18 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
19 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
20 {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
21 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
22 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
29 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
35 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
36 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
37 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
38 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
[all …]
/u-boot/board/compulab/cm_t43/
A Dmux.c18 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE | PULLDOWN_EN},
19 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE | PULLDOWN_EN},
20 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE | PULLDOWN_EN},
21 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE | PULLDOWN_EN},
22 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE | PULLDOWN_EN},
23 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE | PULLDOWN_EN},
44 {OFFSET(mdio_data), (MODE(0) | PULLUP_EN | RXACTIVE)},
74 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
75 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
76 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
[all …]
/u-boot/board/BuR/brppt1/
A Dmux.c79 {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
80 {OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
101 {OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
106 {OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
107 {OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
108 {OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
109 {OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
145 {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
147 {OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
149 {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
[all …]
/u-boot/board/bosch/shc/
A Dmux.c111 {OFFSET(ntrst), (MODE(0) | RXACTIVE)},
177 {OFFSET(mii1_col), MODE(0) | RXACTIVE},
178 {OFFSET(mii1_crs), MODE(0) | RXACTIVE},
179 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
181 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
184 {OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
185 {OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
188 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
189 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
190 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
[all …]
/u-boot/board/phytec/phycore_am335x_r2/
A Dmux.c36 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
38 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
46 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
48 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
49 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
56 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
57 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
61 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
65 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
[all …]
/u-boot/board/tcl/sl50/
A Dmux.c77 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
79 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
85 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
87 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
93 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
95 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
100 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
102 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
103 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
104 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
[all …]
/u-boot/board/BuR/brsmarc1/
A Dmux.c21 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
23 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
25 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
35 {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
37 {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE},
39 {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
51 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
59 {OFFSET(uart0_rtsn), MODE(2) | RXACTIVE},
81 {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
93 {OFFSET(emu0), (MODE(7) | PULLUDDIS | RXACTIVE)},
[all …]
/u-boot/board/vscom/baltos/
A Dmux.c41 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
43 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
49 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
53 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
54 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
63 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
69 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
70 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
71 {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
72 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
[all …]
A Dboard.c338 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
339 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
340 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
341 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
/u-boot/board/isee/igep003x/
A Dmux.c23 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
33 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
34 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
35 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
40 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
41 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
60 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
61 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
62 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
63 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
[all …]
/u-boot/board/BuR/brxre1/
A Dmux.c20 {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
22 {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
24 {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
36 {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE},
44 {OFFSET(uart1_txd), MODE(2) | RXACTIVE},
58 {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)},
60 {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)},
66 {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
80 {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)},
105 {OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
[all …]
/u-boot/board/compulab/cm_t335/
A Dmux.c17 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
23 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
25 {OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
63 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
[all …]
/u-boot/board/bosch/guardian/
A Dmux.c18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
33 {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
44 {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
45 {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
46 {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
47 {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
48 {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
49 {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
50 {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
51 {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
[all …]
/u-boot/board/siemens/pxm2/
A Dmux.c25 {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
67 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
73 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
74 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
75 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
76 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
77 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
85 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
91 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
92 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
[all …]
/u-boot/board/grinn/chiliboard/
A Dboard.c35 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
41 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
42 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
45 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
46 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
51 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
52 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
56 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
57 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
58 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
[all …]
/u-boot/arch/arm/mach-omap2/am33xx/
A Dchilisom.c30 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
32 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
38 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
39 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
40 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
41 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
42 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
43 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
44 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
45 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
[all …]
/u-boot/board/eets/pdu001/
A Dmux.c19 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
25 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
31 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
37 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
43 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
49 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
55 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
57 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
/u-boot/arch/arm/include/asm/arch-am33xx/
A Dmux_am43xx.h18 #define RXACTIVE (0x1 << 18) macro
A Dmux_am33xx.h26 #define RXACTIVE (0x1 << 5) macro

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