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Searched refs:S0 (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/x86/include/asm/arch-apollolake/acpi/
A Dxhci.asl11 Name (_S0W, 3) /* D3 can wake device in S0 */
A Dpcie_port.asl9 * PCIe root port during S0 state
A Dscs.asl117 Name (_S0W, 4) /* _S0W: S0 Device Wake State */
/u-boot/lib/
A Dsha256.c84 #define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3)) in sha256_process() macro
96 S0(W[t - 15]) + W[t - 16] \ in sha256_process()
/u-boot/arch/arm/dts/
A Drk3399-gru.dtsi652 * At the moment settings are identical for S0 and S3, but if we later
/u-boot/doc/arch/
A Dx86.rst636 * Support S0/S3/S4/S5, reboot and shutdown from OS.

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