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Searched refs:SCG_PLL_CFG_PLLSEL_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c273 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_apll_get_rate()
301 val = (reg & SCG_PLL_CFG_PLLSEL_MASK) >> SCG_PLL_CFG_PLLSEL_SHIFT; in scg_spll_get_rate()
1062 val &= ~SCG_PLL_CFG_PLLSEL_MASK; in scg_a7_init_core_clk()
1073 val |= SCG_PLL_CFG_PLLSEL_MASK; in scg_a7_init_core_clk()
/u-boot/arch/arm/include/asm/arch-mx7ulp/
A Dscg.h183 #define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT) macro

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