Searched refs:SCLK_UART0 (Results 1 – 25 of 27) sorted by relevance
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| /u-boot/include/dt-bindings/clock/ |
| A D | rk3036-cru.h | 23 #define SCLK_UART0 77 macro
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| A D | rk3128-cru.h | 22 #define SCLK_UART0 77 macro
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| A D | exynos7420-clk.h | 82 #define SCLK_UART0 2 macro
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| A D | rk3228-cru.h | 23 #define SCLK_UART0 77 macro
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| A D | rk3188-cru-common.h | 20 #define SCLK_UART0 64 macro
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| A D | rk3288-cru.h | 29 #define SCLK_UART0 77 macro
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| A D | rk3368-cru.h | 39 #define SCLK_UART0 77 macro
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| A D | rv1108-cru.h | 22 #define SCLK_UART0 72 macro
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| A D | rk3308-cru.h | 21 #define SCLK_UART0 17 macro
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| A D | rk3328-cru.h | 27 #define SCLK_UART0 38 macro
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| A D | rk3399-cru.h | 37 #define SCLK_UART0 81 macro
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-cru.txt | 60 clocks = <&cru SCLK_UART0>;
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| A D | rockchip,rk3188-cru.txt | 60 clocks = <&cru SCLK_UART0>;
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| /u-boot/drivers/clk/rockchip/ |
| A D | clk_rk3328.c | 655 case SCLK_UART0: in rk3328_clk_set_rate()
776 case SCLK_UART0: in rk3328_clk_set_parent()
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| A D | clk_rk3288.c | 890 case SCLK_UART0: in rk3288_clk_set_rate()
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| A D | clk_rk3399.c | 937 case SCLK_UART0: in rk3399_clk_get_rate()
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| /u-boot/arch/arm/dts/ |
| A D | rk3036.dtsi | 117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rk3xxx.dtsi | 121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rv1108.dtsi | 116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rk3128.dtsi | 264 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rk3288-veyron.dtsi | 550 assigned-clocks = <&cru SCLK_UART0>;
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| A D | rk322x.dtsi | 178 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rk3328.dtsi | 346 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
780 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
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| A D | rk3368.dtsi | 387 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| A D | rk3288.dtsi | 327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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