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Searched refs:SCU_MPLL_POST_MASK (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/clk/aspeed/
A Dclk_ast2500.c61 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate()
276 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2500_configure_ddr()
282 mpll_reg &= ~(SCU_MPLL_POST_MASK | SCU_MPLL_NUM_MASK in ast2500_configure_ddr()
/u-boot/arch/arm/include/asm/arch-aspeed/
A Dscu_ast2500.h22 #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) macro

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