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Searched refs:SDMMC1 (Results 1 – 18 of 18) sorted by relevance

/u-boot/arch/arm/dts/
A Dstm32f7-pinctrl.dtsi228 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
229 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
230 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
231 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
232 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
233 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
241 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
242 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
243 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
244 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
[all …]
A Dstm32h743.dtsi329 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
A Dstm32f746.dtsi455 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
/u-boot/arch/arm/mach-tegra/tegra114/
A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
123 PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4),
226 PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4),
281 PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
/u-boot/arch/arm/mach-tegra/tegra124/
A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA),
123 PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI),
283 PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA),
/u-boot/board/nvidia/dalmore/
A Dpinmux-config-dalmore.h165 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
166 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
167 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
168 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
169 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
170 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/u-boot/arch/arm/mach-tegra/tegra30/
A Dpinmux.c43 PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA),
44 PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA),
45 PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA),
46 PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA),
47 PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA),
48 PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA),
/u-boot/board/nvidia/nyan-big/
A Dpinmux-config-nyan-big.h206 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
227 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
228 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
229 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
230 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
231 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
232 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/u-boot/board/nvidia/venice2/
A Dpinmux-config-venice2.h217 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
238 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
239 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
240 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
241 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
242 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
243 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/u-boot/board/toradex/apalis-tk1/
A Dpinmux-config-apalis-tk1.h190 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
211 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
212 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
213 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
214 PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
215 PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
216 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
/u-boot/board/nvidia/cardhu/
A Dpinmux-config-cardhu.h59 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
60 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
61 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
/u-boot/board/toradex/apalis_t30/
A Dpinmux-config-apalis_t30.h61 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT),
65 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT),
66 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT),
/u-boot/board/avionic-design/common/
A Dpinmux-config-tamonten-ng.h60 DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
61 DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
62 DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
63 DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
64 DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
65 DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
/u-boot/include/dt-bindings/clock/
A Dstm32mp1-clks.h121 #define SDMMC1 108 macro
/u-boot/board/cei/cei-tk1-som/
A Dpinmux-config-cei-tk1-som.h202 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
223 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
224 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
225 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
228 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
/u-boot/board/nvidia/jetson-tk1/
A Dpinmux-config-jetson-tk1.h210 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
231 PINCFG(SDMMC1_DAT3_PY4, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
232 PINCFG(SDMMC1_DAT2_PY5, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
233 PINCFG(SDMMC1_DAT1_PY6, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
236 PINCFG(SDMMC1_CMD_PZ1, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
/u-boot/drivers/clk/
A Dclk_stm32f.c453 case STM32F7_APB2_CLOCK(SDMMC1): in stm32_clk_get_rate()
455 if (clk->id == STM32F7_APB2_CLOCK(SDMMC1)) in stm32_clk_get_rate()
/u-boot/arch/arm/mach-tegra/tegra20/
A Dpinmux.c318 PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),

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