1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
5 */
6
7 #define LOG_CATEGORY UCLASS_MMC
8
9 #include <common.h>
10 #include <clk.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <fdtdec.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <asm/bitops.h>
17 #include <asm/cache.h>
18 #include <dm/device_compat.h>
19 #include <linux/bitops.h>
20 #include <linux/delay.h>
21 #include <linux/libfdt.h>
22 #include <mmc.h>
23 #include <reset.h>
24 #include <asm/io.h>
25 #include <asm/gpio.h>
26 #include <linux/iopoll.h>
27 #include <watchdog.h>
28
29 struct stm32_sdmmc2_plat {
30 struct mmc_config cfg;
31 struct mmc mmc;
32 };
33
34 struct stm32_sdmmc2_priv {
35 fdt_addr_t base;
36 struct clk clk;
37 struct reset_ctl reset_ctl;
38 struct gpio_desc cd_gpio;
39 u32 clk_reg_msk;
40 u32 pwr_reg_msk;
41 };
42
43 struct stm32_sdmmc2_ctx {
44 u32 cache_start;
45 u32 cache_end;
46 u32 data_length;
47 bool dpsm_abort;
48 };
49
50 /* SDMMC REGISTERS OFFSET */
51 #define SDMMC_POWER 0x00 /* SDMMC power control */
52 #define SDMMC_CLKCR 0x04 /* SDMMC clock control */
53 #define SDMMC_ARG 0x08 /* SDMMC argument */
54 #define SDMMC_CMD 0x0C /* SDMMC command */
55 #define SDMMC_RESP1 0x14 /* SDMMC response 1 */
56 #define SDMMC_RESP2 0x18 /* SDMMC response 2 */
57 #define SDMMC_RESP3 0x1C /* SDMMC response 3 */
58 #define SDMMC_RESP4 0x20 /* SDMMC response 4 */
59 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
60 #define SDMMC_DLEN 0x28 /* SDMMC data length */
61 #define SDMMC_DCTRL 0x2C /* SDMMC data control */
62 #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */
63 #define SDMMC_STA 0x34 /* SDMMC status */
64 #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */
65 #define SDMMC_MASK 0x3C /* SDMMC mask */
66 #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */
67 #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */
68
69 /* SDMMC_POWER register */
70 #define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0)
71 #define SDMMC_POWER_PWRCTRL_OFF 0
72 #define SDMMC_POWER_PWRCTRL_CYCLE 2
73 #define SDMMC_POWER_PWRCTRL_ON 3
74 #define SDMMC_POWER_VSWITCH BIT(2)
75 #define SDMMC_POWER_VSWITCHEN BIT(3)
76 #define SDMMC_POWER_DIRPOL BIT(4)
77
78 /* SDMMC_CLKCR register */
79 #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0)
80 #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV
81 #define SDMMC_CLKCR_PWRSAV BIT(12)
82 #define SDMMC_CLKCR_WIDBUS_4 BIT(14)
83 #define SDMMC_CLKCR_WIDBUS_8 BIT(15)
84 #define SDMMC_CLKCR_NEGEDGE BIT(16)
85 #define SDMMC_CLKCR_HWFC_EN BIT(17)
86 #define SDMMC_CLKCR_DDR BIT(18)
87 #define SDMMC_CLKCR_BUSSPEED BIT(19)
88 #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
89 #define SDMMC_CLKCR_SELCLKRX_CK 0
90 #define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
91 #define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
92
93 /* SDMMC_CMD register */
94 #define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
95 #define SDMMC_CMD_CMDTRANS BIT(6)
96 #define SDMMC_CMD_CMDSTOP BIT(7)
97 #define SDMMC_CMD_WAITRESP GENMASK(9, 8)
98 #define SDMMC_CMD_WAITRESP_0 BIT(8)
99 #define SDMMC_CMD_WAITRESP_1 BIT(9)
100 #define SDMMC_CMD_WAITINT BIT(10)
101 #define SDMMC_CMD_WAITPEND BIT(11)
102 #define SDMMC_CMD_CPSMEN BIT(12)
103 #define SDMMC_CMD_DTHOLD BIT(13)
104 #define SDMMC_CMD_BOOTMODE BIT(14)
105 #define SDMMC_CMD_BOOTEN BIT(15)
106 #define SDMMC_CMD_CMDSUSPEND BIT(16)
107
108 /* SDMMC_DCTRL register */
109 #define SDMMC_DCTRL_DTEN BIT(0)
110 #define SDMMC_DCTRL_DTDIR BIT(1)
111 #define SDMMC_DCTRL_DTMODE GENMASK(3, 2)
112 #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4)
113 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4
114 #define SDMMC_DCTRL_RWSTART BIT(8)
115 #define SDMMC_DCTRL_RWSTOP BIT(9)
116 #define SDMMC_DCTRL_RWMOD BIT(10)
117 #define SDMMC_DCTRL_SDMMCEN BIT(11)
118 #define SDMMC_DCTRL_BOOTACKEN BIT(12)
119 #define SDMMC_DCTRL_FIFORST BIT(13)
120
121 /* SDMMC_STA register */
122 #define SDMMC_STA_CCRCFAIL BIT(0)
123 #define SDMMC_STA_DCRCFAIL BIT(1)
124 #define SDMMC_STA_CTIMEOUT BIT(2)
125 #define SDMMC_STA_DTIMEOUT BIT(3)
126 #define SDMMC_STA_TXUNDERR BIT(4)
127 #define SDMMC_STA_RXOVERR BIT(5)
128 #define SDMMC_STA_CMDREND BIT(6)
129 #define SDMMC_STA_CMDSENT BIT(7)
130 #define SDMMC_STA_DATAEND BIT(8)
131 #define SDMMC_STA_DHOLD BIT(9)
132 #define SDMMC_STA_DBCKEND BIT(10)
133 #define SDMMC_STA_DABORT BIT(11)
134 #define SDMMC_STA_DPSMACT BIT(12)
135 #define SDMMC_STA_CPSMACT BIT(13)
136 #define SDMMC_STA_TXFIFOHE BIT(14)
137 #define SDMMC_STA_RXFIFOHF BIT(15)
138 #define SDMMC_STA_TXFIFOF BIT(16)
139 #define SDMMC_STA_RXFIFOF BIT(17)
140 #define SDMMC_STA_TXFIFOE BIT(18)
141 #define SDMMC_STA_RXFIFOE BIT(19)
142 #define SDMMC_STA_BUSYD0 BIT(20)
143 #define SDMMC_STA_BUSYD0END BIT(21)
144 #define SDMMC_STA_SDMMCIT BIT(22)
145 #define SDMMC_STA_ACKFAIL BIT(23)
146 #define SDMMC_STA_ACKTIMEOUT BIT(24)
147 #define SDMMC_STA_VSWEND BIT(25)
148 #define SDMMC_STA_CKSTOP BIT(26)
149 #define SDMMC_STA_IDMATE BIT(27)
150 #define SDMMC_STA_IDMABTC BIT(28)
151
152 /* SDMMC_ICR register */
153 #define SDMMC_ICR_CCRCFAILC BIT(0)
154 #define SDMMC_ICR_DCRCFAILC BIT(1)
155 #define SDMMC_ICR_CTIMEOUTC BIT(2)
156 #define SDMMC_ICR_DTIMEOUTC BIT(3)
157 #define SDMMC_ICR_TXUNDERRC BIT(4)
158 #define SDMMC_ICR_RXOVERRC BIT(5)
159 #define SDMMC_ICR_CMDRENDC BIT(6)
160 #define SDMMC_ICR_CMDSENTC BIT(7)
161 #define SDMMC_ICR_DATAENDC BIT(8)
162 #define SDMMC_ICR_DHOLDC BIT(9)
163 #define SDMMC_ICR_DBCKENDC BIT(10)
164 #define SDMMC_ICR_DABORTC BIT(11)
165 #define SDMMC_ICR_BUSYD0ENDC BIT(21)
166 #define SDMMC_ICR_SDMMCITC BIT(22)
167 #define SDMMC_ICR_ACKFAILC BIT(23)
168 #define SDMMC_ICR_ACKTIMEOUTC BIT(24)
169 #define SDMMC_ICR_VSWENDC BIT(25)
170 #define SDMMC_ICR_CKSTOPC BIT(26)
171 #define SDMMC_ICR_IDMATEC BIT(27)
172 #define SDMMC_ICR_IDMABTCC BIT(28)
173 #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0)))
174
175 /* SDMMC_MASK register */
176 #define SDMMC_MASK_CCRCFAILIE BIT(0)
177 #define SDMMC_MASK_DCRCFAILIE BIT(1)
178 #define SDMMC_MASK_CTIMEOUTIE BIT(2)
179 #define SDMMC_MASK_DTIMEOUTIE BIT(3)
180 #define SDMMC_MASK_TXUNDERRIE BIT(4)
181 #define SDMMC_MASK_RXOVERRIE BIT(5)
182 #define SDMMC_MASK_CMDRENDIE BIT(6)
183 #define SDMMC_MASK_CMDSENTIE BIT(7)
184 #define SDMMC_MASK_DATAENDIE BIT(8)
185 #define SDMMC_MASK_DHOLDIE BIT(9)
186 #define SDMMC_MASK_DBCKENDIE BIT(10)
187 #define SDMMC_MASK_DABORTIE BIT(11)
188 #define SDMMC_MASK_TXFIFOHEIE BIT(14)
189 #define SDMMC_MASK_RXFIFOHFIE BIT(15)
190 #define SDMMC_MASK_RXFIFOFIE BIT(17)
191 #define SDMMC_MASK_TXFIFOEIE BIT(18)
192 #define SDMMC_MASK_BUSYD0ENDIE BIT(21)
193 #define SDMMC_MASK_SDMMCITIE BIT(22)
194 #define SDMMC_MASK_ACKFAILIE BIT(23)
195 #define SDMMC_MASK_ACKTIMEOUTIE BIT(24)
196 #define SDMMC_MASK_VSWENDIE BIT(25)
197 #define SDMMC_MASK_CKSTOPIE BIT(26)
198 #define SDMMC_MASK_IDMABTCIE BIT(28)
199
200 /* SDMMC_IDMACTRL register */
201 #define SDMMC_IDMACTRL_IDMAEN BIT(0)
202
203 #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF
204 #define SDMMC_BUSYD0END_TIMEOUT_US 2000000
205
stm32_sdmmc2_start_data(struct udevice * dev,struct mmc_data * data,struct stm32_sdmmc2_ctx * ctx)206 static void stm32_sdmmc2_start_data(struct udevice *dev,
207 struct mmc_data *data,
208 struct stm32_sdmmc2_ctx *ctx)
209 {
210 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
211 u32 data_ctrl, idmabase0;
212
213 /* Configure the SDMMC DPSM (Data Path State Machine) */
214 data_ctrl = (__ilog2(data->blocksize) <<
215 SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
216 SDMMC_DCTRL_DBLOCKSIZE;
217
218 if (data->flags & MMC_DATA_READ) {
219 data_ctrl |= SDMMC_DCTRL_DTDIR;
220 idmabase0 = (u32)data->dest;
221 } else {
222 idmabase0 = (u32)data->src;
223 }
224
225 /* Set the SDMMC DataLength value */
226 writel(ctx->data_length, priv->base + SDMMC_DLEN);
227
228 /* Write to SDMMC DCTRL */
229 writel(data_ctrl, priv->base + SDMMC_DCTRL);
230
231 /* Cache align */
232 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
233 ctx->cache_end = roundup(idmabase0 + ctx->data_length,
234 ARCH_DMA_MINALIGN);
235
236 /*
237 * Flush data cache before DMA start (clean and invalidate)
238 * Clean also needed for read
239 * Avoid issue on buffer not cached-aligned
240 */
241 flush_dcache_range(ctx->cache_start, ctx->cache_end);
242
243 /* Enable internal DMA */
244 writel(idmabase0, priv->base + SDMMC_IDMABASE0);
245 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
246 }
247
stm32_sdmmc2_start_cmd(struct udevice * dev,struct mmc_cmd * cmd,u32 cmd_param,struct stm32_sdmmc2_ctx * ctx)248 static void stm32_sdmmc2_start_cmd(struct udevice *dev,
249 struct mmc_cmd *cmd, u32 cmd_param,
250 struct stm32_sdmmc2_ctx *ctx)
251 {
252 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
253 u32 timeout = 0;
254
255 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
256 writel(0, priv->base + SDMMC_CMD);
257
258 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
259 if (cmd->resp_type & MMC_RSP_PRESENT) {
260 if (cmd->resp_type & MMC_RSP_136)
261 cmd_param |= SDMMC_CMD_WAITRESP;
262 else if (cmd->resp_type & MMC_RSP_CRC)
263 cmd_param |= SDMMC_CMD_WAITRESP_0;
264 else
265 cmd_param |= SDMMC_CMD_WAITRESP_1;
266 }
267
268 /*
269 * SDMMC_DTIME must be set in two case:
270 * - on data transfert.
271 * - on busy request.
272 * If not done or too short, the dtimeout flag occurs and DPSM stays
273 * enabled/busy and waits for abort (stop transmission cmd).
274 * Next data command is not possible whereas DPSM is activated.
275 */
276 if (ctx->data_length) {
277 timeout = SDMMC_CMD_TIMEOUT;
278 } else {
279 writel(0, priv->base + SDMMC_DCTRL);
280
281 if (cmd->resp_type & MMC_RSP_BUSY)
282 timeout = SDMMC_CMD_TIMEOUT;
283 }
284
285 /* Set the SDMMC Data TimeOut value */
286 writel(timeout, priv->base + SDMMC_DTIMER);
287
288 /* Clear flags */
289 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
290
291 /* Set SDMMC argument value */
292 writel(cmd->cmdarg, priv->base + SDMMC_ARG);
293
294 /* Set SDMMC command parameters */
295 writel(cmd_param, priv->base + SDMMC_CMD);
296 }
297
stm32_sdmmc2_end_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct stm32_sdmmc2_ctx * ctx)298 static int stm32_sdmmc2_end_cmd(struct udevice *dev,
299 struct mmc_cmd *cmd,
300 struct stm32_sdmmc2_ctx *ctx)
301 {
302 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
303 u32 mask = SDMMC_STA_CTIMEOUT;
304 u32 status;
305 int ret;
306
307 if (cmd->resp_type & MMC_RSP_PRESENT) {
308 mask |= SDMMC_STA_CMDREND;
309 if (cmd->resp_type & MMC_RSP_CRC)
310 mask |= SDMMC_STA_CCRCFAIL;
311 } else {
312 mask |= SDMMC_STA_CMDSENT;
313 }
314
315 /* Polling status register */
316 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
317 10000);
318
319 if (ret < 0) {
320 dev_dbg(dev, "timeout reading SDMMC_STA register\n");
321 ctx->dpsm_abort = true;
322 return ret;
323 }
324
325 /* Check status */
326 if (status & SDMMC_STA_CTIMEOUT) {
327 dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
328 status, cmd->cmdidx);
329 ctx->dpsm_abort = true;
330 return -ETIMEDOUT;
331 }
332
333 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
334 dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
335 status, cmd->cmdidx);
336 ctx->dpsm_abort = true;
337 return -EILSEQ;
338 }
339
340 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
341 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
342 if (cmd->resp_type & MMC_RSP_136) {
343 cmd->response[1] = readl(priv->base + SDMMC_RESP2);
344 cmd->response[2] = readl(priv->base + SDMMC_RESP3);
345 cmd->response[3] = readl(priv->base + SDMMC_RESP4);
346 }
347
348 /* Wait for BUSYD0END flag if busy status is detected */
349 if (cmd->resp_type & MMC_RSP_BUSY &&
350 status & SDMMC_STA_BUSYD0) {
351 mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
352
353 /* Polling status register */
354 ret = readl_poll_timeout(priv->base + SDMMC_STA,
355 status, status & mask,
356 SDMMC_BUSYD0END_TIMEOUT_US);
357
358 if (ret < 0) {
359 dev_dbg(dev, "timeout reading SDMMC_STA\n");
360 ctx->dpsm_abort = true;
361 return ret;
362 }
363
364 if (status & SDMMC_STA_DTIMEOUT) {
365 dev_dbg(dev,
366 "error SDMMC_STA_DTIMEOUT (0x%x)\n",
367 status);
368 ctx->dpsm_abort = true;
369 return -ETIMEDOUT;
370 }
371 }
372 }
373
374 return 0;
375 }
376
stm32_sdmmc2_end_data(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data,struct stm32_sdmmc2_ctx * ctx)377 static int stm32_sdmmc2_end_data(struct udevice *dev,
378 struct mmc_cmd *cmd,
379 struct mmc_data *data,
380 struct stm32_sdmmc2_ctx *ctx)
381 {
382 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
383 u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
384 SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
385 u32 status;
386
387 if (data->flags & MMC_DATA_READ)
388 mask |= SDMMC_STA_RXOVERR;
389 else
390 mask |= SDMMC_STA_TXUNDERR;
391
392 status = readl(priv->base + SDMMC_STA);
393 while (!(status & mask))
394 status = readl(priv->base + SDMMC_STA);
395
396 /*
397 * Need invalidate the dcache again to avoid any
398 * cache-refill during the DMA operations (pre-fetching)
399 */
400 if (data->flags & MMC_DATA_READ)
401 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
402
403 if (status & SDMMC_STA_DCRCFAIL) {
404 dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
405 status, cmd->cmdidx);
406 if (readl(priv->base + SDMMC_DCOUNT))
407 ctx->dpsm_abort = true;
408 return -EILSEQ;
409 }
410
411 if (status & SDMMC_STA_DTIMEOUT) {
412 dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
413 status, cmd->cmdidx);
414 ctx->dpsm_abort = true;
415 return -ETIMEDOUT;
416 }
417
418 if (status & SDMMC_STA_TXUNDERR) {
419 dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
420 status, cmd->cmdidx);
421 ctx->dpsm_abort = true;
422 return -EIO;
423 }
424
425 if (status & SDMMC_STA_RXOVERR) {
426 dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
427 status, cmd->cmdidx);
428 ctx->dpsm_abort = true;
429 return -EIO;
430 }
431
432 if (status & SDMMC_STA_IDMATE) {
433 dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
434 status, cmd->cmdidx);
435 ctx->dpsm_abort = true;
436 return -EIO;
437 }
438
439 return 0;
440 }
441
stm32_sdmmc2_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)442 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
443 struct mmc_data *data)
444 {
445 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
446 struct stm32_sdmmc2_ctx ctx;
447 u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
448 int ret, retry = 3;
449
450 WATCHDOG_RESET();
451
452 retry_cmd:
453 ctx.data_length = 0;
454 ctx.dpsm_abort = false;
455
456 if (data) {
457 ctx.data_length = data->blocks * data->blocksize;
458 stm32_sdmmc2_start_data(dev, data, &ctx);
459 }
460
461 stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx);
462
463 dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%x\n",
464 cmd->cmdidx, data ? ctx.data_length : 0, (unsigned int)data);
465
466 ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx);
467
468 if (data && !ret)
469 ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx);
470
471 /* Clear flags */
472 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
473 if (data)
474 writel(0x0, priv->base + SDMMC_IDMACTRL);
475
476 /*
477 * To stop Data Path State Machine, a stop_transmission command
478 * shall be send on cmd or data errors.
479 */
480 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
481 struct mmc_cmd stop_cmd;
482
483 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
484 stop_cmd.cmdarg = 0;
485 stop_cmd.resp_type = MMC_RSP_R1b;
486
487 dev_dbg(dev, "send STOP command to abort dpsm treatments\n");
488
489 ctx.data_length = 0;
490
491 stm32_sdmmc2_start_cmd(dev, &stop_cmd,
492 SDMMC_CMD_CMDSTOP, &ctx);
493 stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx);
494
495 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
496 }
497
498 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
499 dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx);
500 retry--;
501 goto retry_cmd;
502 }
503
504 dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret);
505
506 return ret;
507 }
508
509 /*
510 * Reset the SDMMC with the RCC.SDMMCxRST register bit.
511 * This will reset the SDMMC to the reset state and the CPSM and DPSM
512 * to the Idle state. SDMMC is disabled, Signals Hiz.
513 */
stm32_sdmmc2_reset(struct stm32_sdmmc2_priv * priv)514 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
515 {
516 /* Reset */
517 reset_assert(&priv->reset_ctl);
518 udelay(2);
519 reset_deassert(&priv->reset_ctl);
520
521 /* init the needed SDMMC register after reset */
522 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
523 }
524
525 /*
526 * Set the SDMMC in power-cycle state.
527 * This will make that the SDMMC_D[7:0],
528 * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
529 * supplied through the signal lines.
530 */
stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv * priv)531 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
532 {
533 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
534 SDMMC_POWER_PWRCTRL_CYCLE)
535 return;
536
537 stm32_sdmmc2_reset(priv);
538 }
539
540 /*
541 * set the SDMMC state Power-on: the card is clocked
542 * manage the SDMMC state control:
543 * Reset => Power-Cycle => Power-Off => Power
544 * PWRCTRL=10 PWCTRL=00 PWCTRL=11
545 */
stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv * priv)546 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
547 {
548 u32 pwrctrl =
549 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK;
550
551 if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
552 return;
553
554 /* warning: same PWRCTRL value after reset and for power-off state
555 * it is the reset state here = the only managed by the driver
556 */
557 if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
558 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
559 priv->base + SDMMC_POWER);
560 }
561
562 /*
563 * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
564 * switch to Power-Off state: SDMCC disable, signals drive 1
565 */
566 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
567 priv->base + SDMMC_POWER);
568
569 /* After the 1ms delay set the SDMMC to power-on */
570 mdelay(1);
571 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
572 priv->base + SDMMC_POWER);
573
574 /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
575 }
576
577 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
stm32_sdmmc2_set_ios(struct udevice * dev)578 static int stm32_sdmmc2_set_ios(struct udevice *dev)
579 {
580 struct mmc *mmc = mmc_get_mmc_dev(dev);
581 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
582 u32 desired = mmc->clock;
583 u32 sys_clock = clk_get_rate(&priv->clk);
584 u32 clk = 0;
585
586 dev_dbg(dev, "bus_with = %d, clock = %d\n",
587 mmc->bus_width, mmc->clock);
588
589 if (mmc->clk_disable)
590 stm32_sdmmc2_pwrcycle(priv);
591 else
592 stm32_sdmmc2_pwron(priv);
593
594 /*
595 * clk_div = 0 => command and data generated on SDMMCCLK falling edge
596 * clk_div > 0 and NEGEDGE = 0 => command and data generated on
597 * SDMMCCLK rising edge
598 * clk_div > 0 and NEGEDGE = 1 => command and data generated on
599 * SDMMCCLK falling edge
600 */
601 if (desired && ((sys_clock > desired) ||
602 IS_RISING_EDGE(priv->clk_reg_msk))) {
603 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
604 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
605 clk = SDMMC_CLKCR_CLKDIV_MAX;
606 }
607
608 if (mmc->bus_width == 4)
609 clk |= SDMMC_CLKCR_WIDBUS_4;
610 if (mmc->bus_width == 8)
611 clk |= SDMMC_CLKCR_WIDBUS_8;
612
613 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
614 priv->base + SDMMC_CLKCR);
615
616 return 0;
617 }
618
stm32_sdmmc2_getcd(struct udevice * dev)619 static int stm32_sdmmc2_getcd(struct udevice *dev)
620 {
621 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
622
623 dev_dbg(dev, "%s called\n", __func__);
624
625 if (dm_gpio_is_valid(&priv->cd_gpio))
626 return dm_gpio_get_value(&priv->cd_gpio);
627
628 return 1;
629 }
630
stm32_sdmmc2_host_power_cycle(struct udevice * dev)631 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
632 {
633 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
634
635 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
636 priv->base + SDMMC_POWER);
637
638 return 0;
639 }
640
641 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
642 .send_cmd = stm32_sdmmc2_send_cmd,
643 .set_ios = stm32_sdmmc2_set_ios,
644 .get_cd = stm32_sdmmc2_getcd,
645 .host_power_cycle = stm32_sdmmc2_host_power_cycle,
646 };
647
stm32_sdmmc2_probe(struct udevice * dev)648 static int stm32_sdmmc2_probe(struct udevice *dev)
649 {
650 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
651 struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
652 struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
653 struct mmc_config *cfg = &plat->cfg;
654 int ret;
655
656 priv->base = dev_read_addr(dev);
657 if (priv->base == FDT_ADDR_T_NONE)
658 return -EINVAL;
659
660 if (dev_read_bool(dev, "st,neg-edge"))
661 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
662 if (dev_read_bool(dev, "st,sig-dir"))
663 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
664 if (dev_read_bool(dev, "st,use-ckin"))
665 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
666
667 ret = clk_get_by_index(dev, 0, &priv->clk);
668 if (ret)
669 return ret;
670
671 ret = clk_enable(&priv->clk);
672 if (ret)
673 goto clk_free;
674
675 ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
676 if (ret)
677 goto clk_disable;
678
679 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
680 GPIOD_IS_IN);
681
682 cfg->f_min = 400000;
683 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
684 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
685 cfg->name = "STM32 SD/MMC";
686
687 cfg->host_caps = 0;
688 cfg->f_max = 52000000;
689 mmc_of_parse(dev, cfg);
690
691 upriv->mmc = &plat->mmc;
692
693 /* SDMMC init */
694 stm32_sdmmc2_reset(priv);
695 return 0;
696
697 clk_disable:
698 clk_disable(&priv->clk);
699 clk_free:
700 clk_free(&priv->clk);
701
702 return ret;
703 }
704
stm32_sdmmc_bind(struct udevice * dev)705 static int stm32_sdmmc_bind(struct udevice *dev)
706 {
707 struct stm32_sdmmc2_plat *plat = dev_get_plat(dev);
708
709 return mmc_bind(dev, &plat->mmc, &plat->cfg);
710 }
711
712 static const struct udevice_id stm32_sdmmc2_ids[] = {
713 { .compatible = "st,stm32-sdmmc2" },
714 { }
715 };
716
717 U_BOOT_DRIVER(stm32_sdmmc2) = {
718 .name = "stm32_sdmmc2",
719 .id = UCLASS_MMC,
720 .of_match = stm32_sdmmc2_ids,
721 .ops = &stm32_sdmmc2_ops,
722 .probe = stm32_sdmmc2_probe,
723 .bind = stm32_sdmmc_bind,
724 .priv_auto = sizeof(struct stm32_sdmmc2_priv),
725 .plat_auto = sizeof(struct stm32_sdmmc2_plat),
726 };
727