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Searched refs:SDRAM_CS_SIZE (Results 1 – 10 of 10) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_sdram.c510 cs_num = (src / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
513 channel.desc->src_addr0 = (src % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
517 cs_num = (dst / (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
521 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
523 channel.desc->dst_addr = (dst % (1 + SDRAM_CS_SIZE)); in ddr3_dram_sram_burst()
A Dddr3_axp.h23 #define SDRAM_CS_SIZE 0xFFFFFFF macro
25 #define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) macro
A Dddr3_init.c175 reg |= (SDRAM_CS_SIZE & 0xFFFF0000); in ddr3_restore_and_set_final_windows()
179 reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000); in ddr3_restore_and_set_final_windows()
250 reg |= (SDRAM_CS_SIZE & 0xFFFF0000); in ddr3_save_and_set_training_windows()
254 reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000; in ddr3_save_and_set_training_windows()
A Dddr3_dqs.c338 sdram_offset = cs_count * (SDRAM_CS_SIZE + 1); in ddr3_find_adll_limits()
980 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS + in ddr3_special_pattern_i_search()
1136 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS; in ddr3_special_pattern_ii_search()
1344 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
1359 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_dqs_patterns()
A Dddr3_read_leveling.c457 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_rl_mode()
811 sdram_offset = cs * (SDRAM_CS_SIZE + 1) + SDRAM_RL_OFFS; in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_pbs.c1569 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
1579 sdram_addr = (cs_count * (SDRAM_CS_SIZE + 1) + in ddr3_load_pbs_patterns()
A Dddr3_write_leveling.c266 tmp_count * (SDRAM_CS_SIZE + 1) + in ddr3_wl_supplement()
/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_plat.h17 #define SDRAM_CS_SIZE 0xfffffff /* FIXME: implement a function for cs size for each platform */ macro
A Dmv_ddr_plat.c1187 reg |= (SDRAM_CS_SIZE & 0xffff0000); in ddr3_save_and_set_training_windows()
1191 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) & in ddr3_save_and_set_training_windows()
A Dddr3_training_leveling.c1391 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern)); in ddr3_tip_xsb_compare_test()

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