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Searched refs:SDR_PHYGRP_RWMGRGRP_ADDRESS (Results 1 – 2 of 2) sorted by relevance

/u-boot/drivers/ddr/altera/
A Dsequencer.c16 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
867 SDR_PHYGRP_RWMGRGRP_ADDRESS | in delay_for_n_mem_clocks()
892 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_init_load_regs()
1251 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_write_test_issue()
1400 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_test_patterns()
1473 SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_load_patterns()
1553 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_test()
1557 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_test()
1560 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | in rw_mgr_mem_calibrate_read_test()
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A Dsequencer.h87 #define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000) macro

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