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Searched refs:SD_97500KHZ (Results 1 – 13 of 13) sorted by relevance

/u-boot/board/renesas/gose/
A Dgose.c59 #define SD_97500KHZ 0x7 macro
69 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
70 writel(SD_97500KHZ, SD2CKCR); in board_early_init_f()
A Dgose_spl.c30 #define SD_97500KHZ 0x7 macro
365 writel(SD_97500KHZ, SD2CKCR); in board_init_f()
/u-boot/board/renesas/koelsch/
A Dkoelsch.c61 #define SD_97500KHZ 0x7 macro
71 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
72 writel(SD_97500KHZ, SD2CKCR); in board_early_init_f()
A Dkoelsch_spl.c30 #define SD_97500KHZ 0x7 macro
362 writel(SD_97500KHZ, SD2CKCR); in board_init_f()
/u-boot/board/renesas/lager/
A Dlager.c70 #define SD_97500KHZ 0x7 macro
80 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
81 writel(SD_97500KHZ, SD2CKCR); in board_early_init_f()
A Dlager_spl.c30 #define SD_97500KHZ 0x7 macro
353 writel(SD_97500KHZ, SD2CKCR); in board_init_f()
/u-boot/board/renesas/alt/
A Dalt.c55 #define SD_97500KHZ 0x7 macro
63 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
A Dalt_spl.c30 #define SD_97500KHZ 0x7 macro
368 writel(SD_97500KHZ, SD1CKCR); in board_init_f()
/u-boot/board/renesas/silk/
A Dsilk.c56 #define SD_97500KHZ 0x7 macro
64 writel(SD_97500KHZ, SD1CKCR); in board_early_init_f()
A Dsilk_spl.c30 #define SD_97500KHZ 0x7 macro
382 writel(SD_97500KHZ, SD1CKCR); in board_init_f()
/u-boot/board/renesas/porter/
A Dporter.c60 #define SD_97500KHZ 0x7 macro
70 writel(SD_97500KHZ, SD2CKCR); in board_early_init_f()
A Dporter_spl.c30 #define SD_97500KHZ 0x7 macro
448 writel(SD_97500KHZ, SD2CKCR); in board_init_f()
/u-boot/board/renesas/stout/
A Dstout_spl.c30 #define SD_97500KHZ 0x7 macro
434 writel(SD_97500KHZ, SD2CKCR); in board_init_f()

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