Searched refs:SET_DDR_DLL_CTL3 (Results 1 – 3 of 3) sorted by relevance
| /u-boot/drivers/ram/octeon/ |
| A D | octeon_ddr.c | 2036 SET_DDR_DLL_CTL3(offset_ena, !!change); in change_dll_offset_enable()
2057 SET_DDR_DLL_CTL3(load_offset, 0); in load_dll_offset()
2061 SET_DDR_DLL_CTL3(mode_sel, dll_offset_mode); in load_dll_offset()
2062 SET_DDR_DLL_CTL3(offset, in load_dll_offset()
2065 SET_DDR_DLL_CTL3(byte_sel, byte_sel); in load_dll_offset()
2069 SET_DDR_DLL_CTL3(load_offset, 1); in load_dll_offset()
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| A D | octeon3_lmc.c | 1396 SET_DDR_DLL_CTL3(byte_sel, bytex); in load_dac_override()
1397 SET_DDR_DLL_CTL3(offset, dac_value >> 1); in load_dac_override()
6183 SET_DDR_DLL_CTL3(dll90_byte_sel, ENCODE_DLL90_BYTE_SEL(i)); in lmc_dll()
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| /u-boot/arch/mips/mach-octeon/include/mach/ |
| A D | octeon_ddr.h | 858 #define SET_DDR_DLL_CTL3(field, expr) \ macro
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