Home
last modified time | relevance | path

Searched refs:SET_SEC_JR_ICID_ENTRY (Results 1 – 7 of 7) sorted by relevance

/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
A Dls1088_ids.c17 SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
18 SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
19 SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
20 SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
A Dls2088_ids.c18 SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
19 SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
20 SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
21 SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
A Dlx2160_ids.c21 SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
22 SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
23 SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
24 SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
A Dls1046_ids.c45 SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
46 SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
47 SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
48 SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
A Dls1043_ids.c47 SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
48 SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
49 SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
50 SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
A Dls1028_ids.c24 SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
25 SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
26 SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
27 SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dfsl_icid.h167 #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ macro

Completed in 6 milliseconds