Searched refs:SIFIVE_SPI_REG_CSDEF (Results 1 – 1 of 1) sorted by relevance
30 #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */ macro115 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); in sifive_spi_prep_device()395 spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); in sifive_spi_init_hw()396 writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF); in sifive_spi_init_hw()397 cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF); in sifive_spi_init_hw()398 writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF); in sifive_spi_init_hw()
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