SOC_REGS_PHY_BASE (reference) in projects: u-boot

Searched refs:SOC_REGS_PHY_BASE (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-mvebu/include/mach/
A D	soc.h	`52 #define SOC_REGS_PHY_BASE 0xd0000000 macro 54 #define SOC_REGS_PHY_BASE 0xf0000000 macro 56 #define SOC_REGS_PHY_BASE 0xf1000000 macro 58 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)`
/u-boot/arch/arm/mach-mvebu/armada8k/
A D	dram.c	`23 pregs.regs[1] = SOC_REGS_PHY_BASE; in a8k_dram_scan_ap_sz()`
/u-boot/arch/arm/mach-mvebu/armada3700/
A D	cpu.c	`66 .phys = SOC_REGS_PHY_BASE, 67 .virt = SOC_REGS_PHY_BASE,`
/u-boot/drivers/ddr/marvell/a38x/
A D	ddr_ml_wrapper.h	`16 #define INTER_REGS_BASE SOC_REGS_PHY_BASE`
A D	mv_ddr_plat.h	`19 #define INTER_REGS_BASE SOC_REGS_PHY_BASE`
/u-boot/arch/arm/mach-mvebu/
A D	cpu.c	`428 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); in arch_cpu_init() 429 set_cbar(SOC_REGS_PHY_BASE + 0xC000); in arch_cpu_init()`
/u-boot/drivers/pci/
A D	pci_mvebu.c	`342 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); in mvebu_pcie_probe() 359 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE); in mvebu_pcie_port_parse_dt()`
/u-boot/drivers/ddr/marvell/axp/
A D	ddr3_axp.h	`78 #define INTER_REGS_BASE SOC_REGS_PHY_BASE`

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