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Searched refs:SPLL (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/include/mach/
A Dclk.h17 #define SPLL 7 macro
/u-boot/arch/arm/mach-exynos/
A Dclock.c127 pllreg == SPLL) in exynos_get_pll_clk()
333 case SPLL: in exynos542x_get_pll_clk()
532 sclk = exynos542x_get_pll_clk(SPLL); in exynos542x_get_periph_rate()
1014 sclk = get_pll_clk(SPLL); in exynos5420_get_lcd_clk()
1050 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()

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