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Searched refs:SPRN_L1CSR0 (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
A Drelease.S122 mtspr SPRN_L1CSR0,r2
124 mfspr r3,SPRN_L1CSR0
130 mtspr SPRN_L1CSR0,r3
133 mfspr r3,SPRN_L1CSR0
A Dstart.S758 mtspr SPRN_L1CSR0,r2
760 mfspr r3,SPRN_L1CSR0
766 mtspr SPRN_L1CSR0,r3
769 mfspr r3,SPRN_L1CSR0
/u-boot/arch/powerpc/include/asm/
A Dprocessor.h485 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ macro
733 #define L1CSR0 SPRN_L1CSR0

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