Searched refs:SPRN_L2CSR1 (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/powerpc/include/asm/
A D	processor.h	522 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ macro 740 #define L2CSR1 SPRN_L2CSR1
/u-boot/arch/powerpc/cpu/mpc85xx/
A D	release.S	276 mtspr SPRN_L2CSR1,r3
A D	cpu_init.c	694 mtspr(SPRN_L2CSR1, (32 + 1)); in l2cache_init()

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