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Searched refs:SRDS_PLLCR0_RFCK_SEL_MASK (Results 1 – 8 of 8) sorted by relevance

/u-boot/board/keymile/kmp204x/
A Dkmp204x.c148 actual &= SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/u-boot/board/freescale/corenet_ds/
A Dcorenet_ds.c179 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/u-boot/board/freescale/p2041rdb/
A Dp2041rdb.c207 expected &= SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/u-boot/board/keymile/kmcent2/
A Dkmcent2.c235 if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) { in misc_init_r()
/u-boot/arch/arm/include/asm/arch-ls102xa/
A Dimmap_ls102xa.h324 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/u-boot/arch/powerpc/cpu/mpc85xx/
A Dfsl_corenet_serdes.c405 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel); in p4080_erratum_serdes8()
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
A Dimmap_lsch2.h575 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/u-boot/arch/powerpc/include/asm/
A Dimmap_85xx.h2537 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
2620 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro

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